Problem $4$: Draw an updated datapath for the single cycle RISC$-$V processor that supports all the instructions used in the function F$1$ in problem $1$ only. The updated datapath should no longer support any instructions not needed by F$1.$ Using the delays given in problem $2,$ what would be the maximum clock frequency in this case?$-$ F$1$: L$2$: addi x$9,$ x$0,-5$ add x$10,$ x$0,$ x$9$ SW x$10,20($x$0)$ lw x$11,20($x$0)$ beq x$9,$ X$11,$ L$1$ jal x$0,$ L$2$ lui x$8,65$ auipc x$9,321$ jalr x$9,80($x$1)$ Ll: