Problem #$5(10$ Points$)$: Draw a circuit diagram for a $2-$way set associative cache that can be indexed by bytes which has $8$ blocks with a block size of $8-$bytes. Show the tag$-$match logic and the output byteselect mux. Also, assume that it is a $32-$bit machine and show the number of bits of the address which goes to each multiplexer and tag$-$comparator.

Problem #$6(10$ Points$)$: For the following code snippet, identify all of the RAW, WAW, and WAR hazards. Provide a list for each hazard. Hint, remember that you have to check more than neighbor instructions.

ADD R$1,$ R$2,$ R$3$

SUB R$3,$ R$4,$ R$6$

MUL R$5,$ R$4,$ R$7$

ADDIU R$5,$ R$5,1$

SUB R$6,$ R$3,$ R$9$

ANDI R$2,$ R$1,$ R$9$