Problem $5($Cache Organization$)$

You are given the following design parameters, fill in the table:

$1.$ All memory addresses are $32-$bit long;

$2.$ A $64$ Kbyte $(\backslash (2^\{\backslash$wedge$\}16\backslash )$ byte$)$ cache is added between the processor and the memory. $(64$ Kbytes do not include the amount of space used to store tags and status bits$)$;

$3.$ There are two associativity choices for the cache: direct$-$mapped and $2-$way set associative. There is a $\backslash (20\backslash \%\backslash )$ increase in cache access time and a $\backslash (40\backslash \%\backslash )$ miss rate reduction when moving from a direct$-$mapped cache to a $2$ way set associative cache;

$4.$ There are two cache block size choices of $16$bytes and $32$bytes. It takes $20$ ns to retrieve $16$bytes of data from the main memory and $25$ ns to retrieve $32$ bytes of data. The cache returns the value to the processor after the entire cache block is filled. However, the cache miss rate is reduced by $\backslash (25\backslash \%\backslash )$ when the cache block size doubles;

$5.$ It takes $10$ ns to access a $64$ Kbyte direct$-$mapped cache;

$6.$ The cache miss rate for a $64$ Kbyte direct$-$mapped cache is $\backslash (10\backslash \%\backslash ).$