Question: Problem 5 : Consider a 6 - stage MIPS pipelined processor with the following stages: IF , ID , EX , MEM, BR , WB

Problem

5

Consider a

6 -

stage MIPS pipelined processor with the following stages: IF

,

,

,

MEM, BR

,

.

In the BR

(

Branch Resolution

)

stage, both the branch target and the branch decision are resolved. Below is the assembly code for the function declared as: tomato

(

int array

[],

int

x,

int

y) .

Assume that the function is called as tomato

(

myarray

, 0, 1199) .

Which assumption is better choice in terms of reducing the number of stall

/

flush cycles in this pipelined execution:

Assuming branches are "predicted as not taken"

Assuming branches are "predict as taken"

Assuming

"

no prediction" strategy where pipeline stalls in the ID stage till branches are resolved in the BR stage

Justify by calculating the total number of stall

/

flush cycles related to the branch assumption. Do not conduct dependency analysis. This question is all about stalls and flushes related to the branch scheme.

Problem 5 : Consider a 6 - stage MIPS pipelined

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