Problem A$.$ A $4-$issue superscalar microprocessor provides out$-$of$-$order issue capabilities on $4$ functions units. The execution of three independent threads, A$,$ B$,$ and C is illustrated in the following table. Each row represents a time slot. A$1,$ A$2,...,$ B$1,$ B$2,...,$ C$1,$ C$2,...,$ are the instructions of the corresponding threads. Each row represents a CPU Clock Cycle.

Long hall stalls: Within a thread, NO instruction is issued on ANY function unit in two or more continuous time slots.

time slots Thread A Thread B Thread C

Issue$1$ Issue $2$ Issue $3$ Issue $4$ Issue$1$ Issue $2$ Issue $3$ Issue $4$ Issue$1$ Issue $2$ Issue $3$ Issue $4$

A$1$ A$4$ A$6$ B$1$ C$1$ C$2$ C$4$ C$5$

A$2$ A$5$ B$2$ B$4$ C$3$

A$3$ A$8$ A$9$ A$10$

A$7$ B$3$ B$6$ B$7$

B$5$ C$6$ C$7$ C$9$

B$8$ C$8$ C$10$

B$9$ C$11$

A$11$ A$13$ A$14$ C$12$

A$12$ A$15$

Referring to the algorithms given on the PPT slides on Multithreading, draw COMPLETE time$/$issue$-$slot graphs to illustrate how each of the following CPU organization issues the instructions of three threads. $($hint: the diagrams on slide $11$ for CMT$,$ FMT$,$ and SMT are NOT complete$)$

a$)$ CPU SS$\_$CMT: a $4-$issue superscalar that supports coarse multithreading

b$)$ CPU SS$\_$FMT: a $4-$issue superscalar that supports fine multithreading

c$)$ CPU SS$\_$SMT: a $4-$issue superscalar that supports simultaneous multithreading