Problem Statement $-$ Build a simple traffic light controller state machine and simulate your state

machine in Verilog. Your design must include $($a$)$ Solution steps, state table, state diagram, schematic of

the Traffic controller and Verilog Simulation.

Description of Problem:

A busy highway is intersected by a little used farm road. Detectors C sense the presence of cars waiting

on the farm road. With no car on farm road, light remain green in highway direction. If vehicle on the

farm road, highway lights go from Green to Yellow to Red, allowing the farm road lights to become

green. These stay green only as long as a farm road car is detected but never longer than a set interval.

When these are met, farm lights transition from Green to Yellow to Red, allowing highway to return to

green. Even if farm road vehicles are waiting, highway gets at least a set interval as green. Assume you

have an interval timer that generates a short time pulse $($TS$)$ and a long time pulse $($TL$)$ in response to a

set $($ST$)$ signal. TS is to be used for timing yellow lights and TL for green lights.

Picture of Highway$/$Farm road Intersection

Design Requirements:

Your design must obey the following rules:

When the light is green on A Street and a car is waiting on B Street, give A Street a yellow light for one

clock cycle and then give A Street a red light and B Street a green light for at least two cycles.

When the light is green on A Street and there is no car on B Street, leave the light green on A Street.

When the is green on B Street $($and we've finished the two cycles from step $1)$ and a car is waiting on

A Street, give B Street a yellow light for one clock cycle and then give B Street a red light and A Street a

green light for at least two cycles.

When the light is green on B Street and there is no car on A Street, leave the light green on B Street.

When you press the reset switch, after no more than six cycles, the light should be initially green on A

Street and red on B Street and the controller should be ready for operation.

please provide explanation to each step and truth table and if you could provide some screenshots of the verilog simulation. thank you