Question: In this problem we assume that the logic blocks used to implement a processor's datapath have the following latencies: I-Mem/D-Mem Register File Adder Register Rea


In this problem we assume that the logic blocks used to implement a processor's datapath have the following latencies: I-Mem/D-Mem Register File Adder Register Rea 150 Register Set up Sign exten 20 ux contro 150 25 200 50 10 Assume that: 1) The delay of any signle gate is 5 ps; 2) "Register read" is the time needed after the rising clock edge for the new register value to appear on the output. This value applies to the PC only 3) "Register setup" is the amount of time a registers data input must be stable before the rising edge of the clock. This value applies to both the PC and Register File Add ALU Shift Uncondbrancheft 2 MemRead Memto Instruction [31-21] RegWrite instruction [9-5] nstruction [20-16 register 1 Read Read PCaddress Read dt register 2 Instruction 131-0 Wirite Read register data 2 ALU ALUAddress data M Instructionnehuckoe Instruction [4-0 data Registers Data Instruction [31-0] 32 64 ALU extend trol Instruction 131-211 Although the control unit as a whole requires 50 ps, it so happens that we can extract the correct value of the Reg2Loc control wire directly from the instruction. Thus, the value of this control wire is available at the same time as the instruction. Explain how we can extract this value directly from the instruction Hints: Carefully examine the opcodes shown in Figure 2.20 in the textbook. Also, remember that LSR and LSL do not use the Rm field. Finally, ignore STXR In this problem we assume that the logic blocks used to implement a processor's datapath have the following latencies: I-Mem/D-Mem Register File Adder Register Rea 150 Register Set up Sign exten 20 ux contro 150 25 200 50 10 Assume that: 1) The delay of any signle gate is 5 ps; 2) "Register read" is the time needed after the rising clock edge for the new register value to appear on the output. This value applies to the PC only 3) "Register setup" is the amount of time a registers data input must be stable before the rising edge of the clock. This value applies to both the PC and Register File Add ALU Shift Uncondbrancheft 2 MemRead Memto Instruction [31-21] RegWrite instruction [9-5] nstruction [20-16 register 1 Read Read PCaddress Read dt register 2 Instruction 131-0 Wirite Read register data 2 ALU ALUAddress data M Instructionnehuckoe Instruction [4-0 data Registers Data Instruction [31-0] 32 64 ALU extend trol Instruction 131-211 Although the control unit as a whole requires 50 ps, it so happens that we can extract the correct value of the Reg2Loc control wire directly from the instruction. Thus, the value of this control wire is available at the same time as the instruction. Explain how we can extract this value directly from the instruction Hints: Carefully examine the opcodes shown in Figure 2.20 in the textbook. Also, remember that LSR and LSL do not use the Rm field. Finally, ignore STXR
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