Problerh solving: - logic gates and machine code 1) Given the following memory dump, using the machine code we introduced in class and with the program counter pointing at memory 6, which is where your code starts (remember memory starts at 0 but may include data), what value will accumulator (RO) hold after the code below executes (show work). Look at Fetch Execute-template for help - use it to keep track of what's going on by filling it in (you can use multiple sheets). Memory dump follows. (in hex...convert to binary). Remember that memory is addressed at the byte level so after each 8 bits (hex pairs) you increment address (i.e., the memory dump below runs from address 0 to address 27)| 00 00 00 32 00 19 41 00 64 46 00 02 76 00 04 56 00 02 DA 00 02 81 00 01 39 00 09 10 1 1 1 11 Fetch-Execute Cycle Given state of memory and assuming instruction start afterwards, we will determine what the Accumulator (register Ro) value will be after executing the machine langunge code using the template to the left to fill in the values for the Instruction Register, Processor Register and Program Counter for each instruction step. addressing modes Program 00: use accumulator (RO) - 8 bit Counter 01: immediate e value) - 24 bit (decimal) 10: direct we value as address) - 24 bit Instruction reg-ister Register adid 00: register RO (accumulator) (binary) 01: register R1 10: register R2 Register RO Register RI instruction code is either RO, immediate, direct) Register R2 0000: NOP - no operation fregaddr ignored) (binary) 0001: HLT - halt execution (reg/addr ignored) 0010: JMP X - goto addr X freg ignored) Program 0011: JMZ reg, X - if reg is o goto addr X Counter 0100: LOD reg. X - load X into reg (decimal 0101: STO reg, X-store reg into X (no immediate) 0110: ADD reg, X-add X to reg Instruction 0111: SUB reg, X - subtract X from reg Register reg addr 1000: MUL reg. X-multiply reg by X (binary) 1001: DIV reg. X. divide reg by X 1010: AND reg. X-if X or reg 0, reg else reg 1 Register RO 1011: OR reg. X - if both X and reg 0, reg else reg 1 Register Ri 1100: NOT reg - invert reg (addr ignored) Register R2 1101: CPZ reg. X - if X is 0, reg 1 else reg 0 (binary) 1110: CPL reg. X-if X less 0, reg 1 else reg 0 address memory Program 0 Counter 1 (decimal) 2 Instruction 3 Register ney add (binary) 4 5 Register RO Register R1 6 Register R2 7 (binary) 8 Program 9 Counter 10 (decimal) 11 Instruction Register reader 12 (binary) 13 15