Question: With a resource allocation constrained to one multiplier/divider, one subtractor, and one shift to perform the multiplication by 2 , derive the Verilog design of

With a resource allocation constrained to one multiplier/divider, one subtractor, and

With a resource allocation constrained to one multiplier/divider, one subtractor, and one shift to perform the multiplication by 2 , derive the Verilog design of the FDA that computes the equation: c=52x5x2y Find: (1) Algebraic transformation (if required), (2) The DFG, (3) Operation scheduling and resource allocation, (3) RTL codes, (4) FBD of Datapath and Controller, (5) Verilog codes, (6) Simulation results (7) Discussion of your design and the results that you obtained

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