Consider a memory system with a two-level hierarchy with a cache M1 and main memory M2. Size of the main memory, M2 is 256 bytes with block size of 16 bytes. Size of the cache, Ml is 64 bytes with the same block size of 16 bytes. The word length is 4 bytes, implying 4 words per block. A sample trace program generates the following sequence of word 0,8,1,16,20,21,24,32,61,3,31,19,60,16,11,22,19,8,28,21,42,28,59,58,55 Note, every time a new block is accessed by the cache, up to 4 words are received implying that if block 0 is accessed from the main memory then 0,1,2,3 words are obtained and so on. The addresses given above are word addresses, not memory block addresses. a Consider a fully associative cache with LRU replacement policy. Determine the hit b) Consider a direct mapped cache. Determine the hit ratio