Provide system Verilog code for a Multiplexed Display to display 5,6,7,8 on a 4-digit-7- segment display: Design Ideas: Your system Verilog code will need a clock divider that controls a digit counter. The digit counter will change once per clock period (as given above). For the example period given above the divider would count down from 50x106/4-178 1 70 224 to zero. Your digit counter can sequence over the enable values (e.g. 4'b0001, 4'b1000, 4'b0100, 4'b0010) or over a value that represents the digit of your ID (e.g. 3, 2, 1, 0). The digit counter value is then used to enable the correct digit enables (unless you used the enable value as the counter values) and the correct segment enables. This can be done with multiplexers or lookup tables. LED Pin wire seg. colour ment CPLD pin top side of display LD5643B 12 en[3] 11 a 10f 9 en[2] 8 en(1) 7b 1 black e 2 brown d 3 red dp 4 orange 5 yellow 9 6 green en[@] 7 blue 8 violet en[1] 9 gray en[2] 10 white f 11 black 12 brown en[3] 30 34 36 38 40 42 44 48 50 52 33 97' h01 17h4f 2 7'h12 3 7'h06 4 7' h4c 5 7'h24 6 7'h20 77' hof 8 7h00 9 7'904 b e 1 ZP dp 13 C14 g|5 en[0] 6 a part number 35 last digit of your ID 0 1 2 3 4 digit sequence 3,0, 1, 2 1, 2, 0,3 0, 1, 2, 3 0, 1, 3,2 2, 1, 3,0 2, 1, 3,0 1, 2, 0, 3 0, 2, 1, 3 0, 3, 2, 1 2, 0, 3, 1 5 6 7 8 9 For example, if your ID was A12345678 then you would assert eno (rightmost digit), then en3 (left- most), then en2 and finally en1. This sequence would repeat at 178 Hz and each digit would be turned on for 1.4 ms at a time (1/(4.178)). 5608 Requirements: Your circuit should show the 5,6,7,8 on the display. Each digit should be displayed at a frequency of 100 + n Hz where n is the last two digits of your ID number. Since there are four digits, your circuit must divide the 50 MHz clock by 50 x 106/(4.(100+n))