Q$1.($a$)$ Design a stick $($layout$)$ diagram for the following static CMOS logic gate, where $\backslash ($ A$,$ B$,$ C$,$ D $\backslash )$ are the logic gate inputs and $\backslash ($ O $/$ P $\backslash )$ is the output:

rigure $1$

Use dual$-$well, CMOS technology. Include wells, well$-$taps, contact cuts, routing of power and GND in your diagram. Use colour coding and$/$or clear and readable detailed annotations to represent the wires in the different layers.