Question: [CLO-1, C3 Application, PLO-2 Problem Analysis] Consider the 8-stage pipelined processor with two execution units and pipelined caches, as shown below. Instruction fetch is a
[CLO-1, C3 Application, PLO-2 Problem Analysis] Consider the 8-stage pipelined processor with two execution units and pipelined caches, as shown below. Instruction fetch is a two-stage process followed by decode where registers are also read in the second half of the cycle. Additionally, the pipeline consists of a separate execution unit for floating point (FP) operations. First unit has a single stage and is used by all integer arithmetic (excluding multiply), load/store and branch instructions. Second unit, of four stages, is used by floating point (FP) add/sub and multiply (both integer and FP) instruetions. The data cache has bus width of 64 bits and takes three stages for read/write operations. The final stage performs registers writes in the first half of the cycle, if required. Consider the clock cycle time for the above pipeline to be 200ps. i. Compute the latency of "LD" Instruction, which loads a double precision floating point number from memory. ii. Assuming there are no FP and multiply instructions in a program, comparing with a fivestage MIPS pipeline compute how fast can the program run on the 8 -stage processor. Assume the cycle time for MIPS is 400 ps, and no extra stall cycles are inserted due to hazards. ii. For a program-A, 30% instructions are dependent floating-point instructions. Assuming no forwarding paths are available, calculate the addition to the CPI due to these hazards. iv. For a program-B, 20% instructions are branches dependent on an integer arithmetic instruction just preceding them and 5% are branches not dependent on a preceding instruction. Of all branches, 80% are taken branches. Branch condition is evaluated in the EX-stage and branch target address is computed in the ID-stage. Again, assuming no forwarding paths are available, compute the addition to the CPI due to these hazards. What types of hazards are present here? v. For the given processor, determine how many stall cycles are required between a load instruction and the different classes of instructions that use the load's result during the execution stage
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