Q$1)$ For a direct$-$mapped cache design with a $32-$bit address, the following bits of the address are used to access the cache: Tag Index Offset $31-109-54-0$ a$)$ What is the cache block size $($in words b$)$ How many entries does the cache have? c$)$ Starting from power on$,$ the following byte$-$addressed cache references are recorded $($addresses are in decimal$)$: $0,4,16,132,232,160,1024,30,140,3100,180,2180$ c$\mathrm{.}1)$ How many blocks are replaced? c$\mathrm{.}2)$ What is the hit ratio?