Q$2.$ Consider the circuit given in Fig $1.$ Assume that each inverter takes $1$ time unit. Assume that it takes $1$ time unit for a pull$-$up path or pull$-$down path to pull$-$up or pull$-$down, respectively. Ignore any leakage effects. Assume $\backslash ($ V$\_\{$D D$\}\backslash$gg V$\_\{$T$\}\backslash ).$ Also, assume that there is no skew between CLK and CLK$\text{'}$ and the rise$/$fall times on all signals are zero. Complete the timing diagram below.

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