Q. 3. A possible reduced instruction set machine might support the following instructions: (8+3 + 2 +2-15 points) ADD rd, rs, rt NAND rd, rs, rt LUI rd, imm BEQ rs, rt, addr LW rd, (rt) . SW rs, (rt) LLI rd, imm JALR rd, rs Suppose that this machine has 8 general purpose registers. Also fields on LUI and LLI can hold any integer from 128 to 127The width of the opcode field is the same for every instruction. suppose that the immediate operand LUI (load upper immediate) and LLI (load lower immediate) allow an immediate number to boe loaded into a register. LUI loads the immediate number into the exact upper half of the register specified by rd while LLI loads the immediate number into the exact lower half of rd. Assume that no instructions beside LUI and LLI are needed to get an immediate number into a register, and assume that the immediate field is the same size in LLI and LUI (a) Ignoring BEQ, how many bits are needed in the instruction word to support all of these instructions? (b) If the instruction word is to contain as few bits as possible, how many bits is the BEQ instruction's address field? Assuming that BEQ uses relative addressing, how many instructions ahead can it branch to? (Consider that BEQ can branch backwards as well as forwards and assume that the BEQ PC-relative displacement value is the number of instructions of displacement.).* Relative addressing is when the address to j current or next PC value.* ump to is an offset stored in the instruction from the (c) How many bits are stored in each general purpose register? (d) If LW and SW use register indirect addressing, how many addresses can this machine index? (Register indirect addressing is when the address to be accessed is stored in a register.)