Q$4)(25$ pts$)$ Consider the following sequence of instructions, and assume that it is executed on a $5-$stage

pipelined data path $($IF$,$ D$/$R$,$ ALU, DM$,$ WB$.$ Also assume that writing into a register happens in the first

half of the clock cycle while reading from a register happens in the second half of the clock cycle:

List the read$-$after$-$write data dependencies. As an example, $x$ on $y($$$t5)$ shows instruction $x$ has data

dependency on instruction y since it is reading register $$t5.$

Assume the $5-$stage MIPS pipeline with no forwarding, what is the total number of stall cycles? What is

the execution time $($in cycles$)$ for the whole program? Show your work.

Assume the $5-$stage MIPS pipeline with full forwarding, what is the total number of stall cycles? What is

the execution time $($in cycles$)$ for the whole program? Show your work.