Q$4)(25$ pts$)$ Consider the following sequence of instructions, and assume that it is executed on a $5-$stage pipelined data path $($IF$,$ D$/$R$,$ ALU, DM$,$ WB$.$ Also assume that writing into a register happens in the first half of the clock cycle while reading from a register happens in the second half of the clock cycle:

$\backslash$table$[[$Iw $t$1,100($$t$5),$# I$1],[$add $t$1,$$t$0,$$t$1,$#$|2|$