Q$.5.$

a$)$ Define a basic $4-$stage pipeline for a RISC processor: Instruction Fetch $($IF$),$ Instruction

Decode & Operand Fetch $($DOF$),$ Execute $($EX$),$ Write Back $($WB$)$ using Pipeline Execution

Pattern.

b$)$ Define the $3$ types of RISC Instruction Register formats with $32-$bit instructor register as an

example. Where $7-$bits are for opcode, and rest of the bits for destination, source and

immediate operands registers.

c$)$ Explain how pipelining can improve the overall throughput of the processor compared to a

single$-$cycle design. Discuss the concept of Instruction Per Cycle $($IPC$)$ and how pipelining

can potentially increase IPC.

d$)$ Identify and explain two potential hazards that can occur in a pipelined processor. Discuss

techniques for mitigating data hazards.

Marks$)$