Q1. Consider a small computing system with a customized 27 bits ISA CPU for the following MIPS Codes: Iw $t0, 0($zero) % load x from Memory add $t1, Szero, zero add $t2, Szero, $zero Ll: beq $t1, $t0, L2% compare i& x (a) Develop the complete single cycle datapath that can execute the above instructions. Show the connectivity, the bus width of the connections in bit(s). (5 marks) (b) Calculate the time period for the CPU, which is designed for 5-stage pipeline operation with the following assumptions- (5 marks) Given that 2 ns for memory data access, 2 ns for ALU operation, 1 ns for register read or write Given that MIPS instruction mix 23% loads, 13% stores, 19% branches, 2% jumps, 43% ALU Q1. Consider a small computing system with a customized 27 bits ISA CPU for the following MIPS Codes: Iw $t0, 0($zero) % load x from Memory add $t1, Szero, zero add $t2, Szero, $zero Ll: beq $t1, $t0, L2% compare i& x (a) Develop the complete single cycle datapath that can execute the above instructions. Show the connectivity, the bus width of the connections in bit(s). (5 marks) (b) Calculate the time period for the CPU, which is designed for 5-stage pipeline operation with the following assumptions- (5 marks) Given that 2 ns for memory data access, 2 ns for ALU operation, 1 ns for register read or write Given that MIPS instruction mix 23% loads, 13% stores, 19% branches, 2% jumps, 43% ALU