Q1. Model the following ALU for n=4 bits using Verilog. Write the Verilog test bench and generate and verify the associated timing in a report to be submitted hard copy. The project should be tested in the lab. Groups of no more than 5 students are allowed. Hint: you can use the Verilog models of the 4-bit adder and 4X1 \& 2X1 MUX from slides in addition to the Verilog models of AND, OR \& exclusive or. Document your code