Q1) Write a VHDL code for the following combinational circuit that performs a circular shift of input A X bits and output the result into B as shown in the figure: [10 Marks Circular_Shift A (3 downto 0) B(3 downtoo) Shift AX bits X(1 downto 0) Q2) Assuming you have the VHDL codes for a 4-1 Multiplexer and a 4 bit up-counter, using only these components, write the top module VHDL code for a programmable clock divider circuit that generates a divided output clock as shown in the table below depending on a presacral input (X): [10 Marks/ cik_div X clk_out clk_in 00 01 clk_in/4 10 clk_in/8 11 clk_in/16 clk_in/ 2clk_out X (1 downtoo) Q3) Design a Moore state machine that implements a sequence counter that counts through the sequence (00 11 10 01 back to 00). The counter has a clock enable (CE) input and a reset. Draw the state diagram and the ASM chart of this counter FSM. [10 Marks Q4) Write the VHDL code for the FSM in Q3. [10 Marks