Q2.A. Complete the behavioral VHDL code to implement the FSM illustrated in the figure below. What is the type of the FSM is it a Mealy or Moore? (7Marks) 2 2x1 MUX ME_O CLK library ieee; use ieee, std_logic_1164.all; entity logic circuit is port(x, clk: in std logic; f: buffer std_logic ); end entity; architecture logic_design of LogicCircuit is signal d, qd temp, t: std_logic:='0'; signal io, il, mux out: std logic; signal qt_temp: std logic; begin