Q$2.$A$.$ Complete the behavioral VHDL code to implement the FSM described in the ASM chart illustrated in

the figure below. What is the type of the FSM is it a Mealy or Moore?

$(6$Marks$)$

els$$t clk$\text{'}$ event and $clk={?}^{\text{'}}1\text{'}$ then

state nextstate;

end if;

end process;

next state logic

Process $($state$,$ a$)$ begin

case state is

when SO $=>$ if $a=\text{'}1\text{'}$ then

nextstate S$1$;

else nextstate SO;

end if;

when S$1=>$ if $a=\text{'}1\text{'}$ then

pextstate S$2$;

else pextstate SO;

end if;

when S$2=>$ if $a=\text{'}1\text{'}$ then

nextstate S$2$;

else nextstate S$3$;

end if;

library ieee;

use ieee.std logic $1164.$a$11$;

entity fsm is

port $($clk$,$ resetn: in std logic;

$s,b,z$ : in std logic;

done, r$,$ q: out std$\_$logic$)$;

end fsm;

architecture behavioral of $fsm$ is

type state is $($S$1,$ s$2,$ s$3)$;

signal y: state;

begin

Transitions: process $($resetn$,$ clk$,$ s$,$ b$,$ z$)$

begin

if resetn $=\text{'}0\text{'}$ then $ys1$;

elsif