Q3. (6 pts) Memory-Mapped IO.

Consider two-data transfer cases: 1) by CPU and 2) by DMAC.

Case 1) CPU-initiated data transfer:

Reading data needs: LDR R0, =src ; 1 cycle

LDR, R1, [R0] ; 2 cycles

3 CPU cycles in total

Writing data needs: LDR R0, =dst ; 1 cycle

STR, R1, [R0] ; 2 cycles

3 CPU cycles in total

Case 2) DMA-initiated data transfer:

DMAC set-up

CPU needs to write to DMAC's four registers: (1) DMA channel 30 (memory-to-memory transfer)s source address end pointer, (2) destination address end pointer, and (3) channel 30s control register to issue a transfer request.

MOV R1, #imm_src_addr ; 1 cycle (parameters definition)

LDR R0, =ch30_src ; 1 cycle

STR, R1, [R0] ; 2 cycles

MOV R1, #imm_dst_addr ; 1 cycle (parameters definition)

LDR R0, =ch30_dst ; 1 cycle

STR, R1, [R0] ; 2 cycles

MOV R1, #imm_cntrl_data ; 1 cycle (parameters definition)

LDR R0, =ch30_cntrl ; 1 cycle

STR, R1, [R0] ; 2 cycles

12 CPU cycles in total

DMAC needs 5 cycles for a 32-bit word transfer from one to another memory.

Now, assume that CPU handles floating-point registers, corresponding to 18 words. Upon receiving an IRQ from DMAC, CPU now needs:

3 cycles to switch its CPU mode

9 cycles to save reqular registers

18 cycles to save floating-point registers

Given the above two scenarios, at least how many words, (32-bit data) should be transferred if CPU takes advantage of DMAC.