Q$3.(6$ pts$)$ Memory$-$Mapped IO$.$

Consider two$-$data transfer cases: $1)$ by CPU and $2)$ by DMAC.

Case $2)$ DMA$-$initiated data transfer:

DMAC set$-$up

CPU needs to write to DMAC's four registers: $(1)$ DMA channel $30($memory$-$to$-$memory transfer$)\text{'}$s source

address end pointer, $(2)$ destination address end pointer, and $(3)$ channel ${30}^{\text{'}}\text{'}$s control register to issue a

transfer request.

$12$ CPU cycles in total

DMAC needs $5$ cycles for a $32-$bit word transfer from one to another memory.

Now, assume that CPU handles floating$-$point registers, corresponding to $18$ words. Upon receiving an IRQ

from DMAC, CPU now needs:

$3$ cycles to switch its CPU mode

$9$ cycles to save reqular registers

$18$ cycles to save floating$-$point registers

Given the above two scenarios, at least how many words, $(32-$bit data$)$ should be transferred if CPU

takes advantage of DMAC.