Question $1,(10$ pts: $2$ points each part$)$

Consider a synchronous sequential circuit that includes two D Flip$-$Flops, where one Flip$-$ Flop's output is $y1$ and the other Flip$-$Flop's output is $y2.$ The circuit has two inputs a and $b,$ one output $Z,$ and is specified by the following next state and output equations.

$Y_1=b+a{y}_2$

$Y_2=y_1+a{y}_2$

$Z=(ao+b)y_1$

a$)$ Draw the logic diagram of the circuit.

b$)$ Derive the state$-$assigned table for the circuit.

c$)$ Derive the state table for the circuit? Is this FSM reducible? $($Hint: name the states$).$

d$)$ Draw the corresponding state diagram.

e$)$ Provide an ASM chart for this circuit.