Question$1-3$:

What is the logic function of the circuits in Figure $1?$

Size the devices so that the output resistance is the same as that of an inverter with an NMOS $\backslash (\backslash$mathrm$\{$W$\}/\backslash$mathrm$\{$L$\}=2\backslash )$ and $\backslash (\backslash$mathrm$\{$PMOS$\}\backslash$mathrm$\{$W$\}/\backslash$mathrm$\{$L$\}=6\backslash ).$

Which input pattern$($s$)$ would give the worst and best equivalent pull$-$up or pull$-$down resistance?

$($Copy the circuit diagram to your exercise book. Some of the gate size is already given$)$

Figure $1$