QUESTION $1$

We will implement the logic function $F^{\text{'}}=A^{\text{'}}BC+D(E+G^{\text{'}}{H}^{\text{'}})$ static CMOS architectures. We will assume input variables and their complements are available at no extra cost. We will also assume that a minimum size transistor contributes capacitance Co through either its drain or gate and capacitance is proportional to width.

a$)$ Implement the gate using the direct method $($i$.$e$.,$ implementing the expression for $F\text{'}$ to get $F$ at the output$)$ using the minimum number of transistors. Arrange transistors so that the minimum number of drains are connected to the output node.

b$)$ Size the pull down network so that the worst case resistance is equal to that of the unit inverter

c$)$ Size the pull up network so that the worst case resistance is equal to that of the pull down network

d$)$ Find the total area of the gate in $65$ nm technology

e$)$ What is the total number of transistors

f$)$ What is the total capacitance at the output node in terms of Co

g$)$ Expand the expression of F using DeMorgan's theory. Implement the gate now using the minimum number of transistors