Question Part

You are given a logic function to implement: X$=$ bar$(($ bar$(($ bar$($A$+$B$))$C$))$D$).$ Limit fan$-$in for a logic gate $($stage$)$ to $3.$ Use the $2$:$1$ sizing rule for each gate. More branched subnets will be closer to the rails this time. Then, series connections will be in alphabetical order towards the output. The transistor connected to output from a previous stage should go closer to the output.

Note: You may zoom out in your browser $($ctrl $+$ wheel, or click the zoom button$).$

Suggestion: Lay out the transistors first in your idea of a good circuit design, then do the wiring.

Note: Do not move or change initial circuit.

Question Part

Now transform the static logic into Domino logic. Size clock transistors to $8,$ inverters to $2,$ and ensure the PDN for each logic stage $($not including the clock$)$ has a worst$-$case sizing of $2($instead of $1).$