Question $1$: Each group will be assigned to ONE $(1)$ of the following combinational logic circuits. Derive the truth table, equation, and circuit theoretically, with

explanation for each design steps. Design the Verilog code for the circuit and show the simulation result for all possible input sequence. Analyze the result in

relation to the operations of the circuit theoretically to verify the Verilog code simulation. $($e$)1$ to $8$ demultiplexer