Question $1$

Write Verilog design code for a module named

add

sub

$4$bit

$,$ which has the below interface:

$$

Inputs:

$$

x

and

y

$-4$ bits: $2$s compliment numbers

$$

add

sub

select

$-1$ bit

$$

Outputs:

$$

z

$-4$ bits: $2$s compliment result

$$

carry

out

$-1$ bit

The testbench for this design has been provided. In this design, when the

add

sub

select

signal

is set to

$0$

$,$ the output

z

should be the sum of the input signals $($

x$+$y

$).$ When

add

sub

select

is

set to

$1$

$,$

z

should be set to

x

$-$

y

$.$

Implement this design using both structural $($using only logic gates like ANDs, ORs, inverters, and

XORs$)$ and behavioral logic. Not that in this module you don$$t need to worry about overflows.

Create separate projects for each implementation of your design. The same testbench

can be used for both projects