Question: Question 2 [ 2 0 Marks ] ( a ) Given the system of Figure 2 . 1 ( i ) Design the value of
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a
Given the system of Figure
i Design the value of as well as in the feedback path of the minor loop, to yield a settling time of seconds with overshoot for the step response.
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ii Design the value of K to yield a majorloop response with overshoot and a peak time of seconds for a step input.
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b
i How can you tell from the root locus if the settling time does not change over a region of gain?
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ii If for what value of gain is s a point on the root locus?
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iii How can you tell from the root locus that the natural frequency does not change over a region of gain?
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iv Why is there more improvement in steadystate error if a PI controller is used instead of a lag network?
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