Question: Question 2 [ 2 0 Marks ] ( a ) Given the system of Figure 2 . 1 ( i ) Design the value of

Question 2
[20 Marks]
(a)
Given the system of Figure 2.1
(i) Design the value of K1, as well as a in the feedback path of the minor loop, to yield a settling time of 4 seconds with 5% overshoot for the step response.
[7 Marks]
(ii) Design the value of K to yield a major-loop response with 10% overshoot and a peak time of 2.3 seconds for a step input.
[5 Marks]
(b)
(i) How can you tell from the root locus if the settling time does not change over a region of gain?
[2 Marks]
(ii) If KG(s)H(s)=25?180, for what value of gain is s a point on the root locus?
[2 Marks]
(iii) How can you tell from the root locus that the natural frequency does not change over a region of gain?
[2 Marks]
(iv) Why is there more improvement in steady-state error if a PI controller is used instead of a lag network?
[2 Marks]
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Question 2 [ 2 0 Marks ] ( a ) Given the system

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