Question $2$: $[20$ points$]$

Consider a CPU which has $20$ bit wide instructions interfaced to a memory in which each location

is $40$ bits wide $($see Figure $2$ next page$).$ This means every location in main memory contains $2$

separate program instructions. If we have $4$ words in main memory, a total of $8$ instructions may

be stored in this memory. A $3-$bit Program Counter is necessary to access each of these $8$ instructions. A $2-$bit wide Memory Address Register will suffice to address the $4$ words. A $20-$bit wide

Instruction Register is needed to store an instruction. Give the details of the $$mystery component$$ hardware which is needed so that the Instruction Register is loaded with the appropriate

instruction. Formulate a procedure which may be used to FETCH and EXECUTE instructions on

this organization. Express your procedure similar to what we have done in class, i$.$e$.$:

T$0$: load MAR with PC

T$1$: read from memory and load instruction into IR

T$2$: $$execute$$ the instruction

$...$

Of course, this is only meant as an example, your solution will be different. You may assume that

the $$execute$$ phase of an instruction may be done in one clock cycle, you do not have to show the

details of the $$execute$$ phase. We are interested in the procedure used to successively load the

Instruction Register with the low$-$order and high$-$order $20-$bit instructions stored in a given $40-$bit

word stored in one location of the memory.

I need the Fetch$-$execute cycle to be written in Register Transfer notation. can you please cinsider this while solving the question. here is the provided photo. Figure $2$: A "wide" memory interfaced to a "narrow" CPU.