Question 2 "timescale ins/ module mux (input 10, 11, sct, output out): vire slet wire out 11 wire out 2: not (slct_n, slot) and out_1, 10. sict_n); and (out_2, II, siet): or (out, out_. out_2); endmodule timescale ina / ips module testbench(): reg 10, 11, let: wire out? integer 1: mux dt (.10(10), 11(11), .slet (slet), out (out)); initial begin 100; 11; 0; Contoz (10t0b 10-0b 11-20 out-0b", slet, 10, 11, out): for(i=0; 18: 1-1+1) begin (slet, 10, 11)-1; 110: end end initial #30 Stina endmodule Which of the following is true for the above 2 verilog codes? 1. Gate design level is used in the code. II. 2x1 Multiplexer is designed in the code. III. All nets in the codes must be defined in the "testbench