Question 2: When processor designers consider a possible improvement to the processor datapath, the decision usually depends on the cost/performance trade-off. In the following three problems, assume that we are starting with a datapath from Figure 4.2, where I-Mem, Add, Mux, ALU, Regs, D-Mem, and Control blocks have latencies and costs as shown in the table Blocks I-Mem, Add Mux ALU Regs D-Mem Control Latency 500 ps 100 ps 50 ps 100 ps 200 ps 300 ps 100 ps Cost 1000 30 10 110 200 2000 500 Consider the addition of a multiplier to the ALU. This addition will add 300 ps to the latency of the ALU and will add a cost of 600 to the ALU. The result will be 25% fewer instructions executed since we will no longer need to emulate the MUL instruction. a. What is the clock cycle time with and without this improvement? b. What is the speedup achieved by adding this improvement? c. What is the total cost with and without this improvement? d. What is the cost ratio achieved by adding this improvement? e. What is the cost/performance ratio achieved by adding this improvement?