Question 2: You need to design a memory system that has 40 bit address bus and 64 bit data bus. The memory system will have 2 cache levels under the RAM. (15 marks) LI cache is a 4-way set associative cache containing 64 KB data and has a line/block size of 256 bits (32 bytes). L2 cache is a 2-way set associative cache containing 2 MB data and has a line/block size of 256 bits (32 bytes). * Design the memory system clearly showing the inter connection between the 2 caches. You should label the tag, index and offset bits clearly with their relevant sizes. Also calculate the size of tag array for each cache