Question $3(10$ points$)$

Consider the following $4-$bit Left Shift Serial In Serial Out $($SISO$)$ register where Time is the clock cycle $($where OT is before the initial clock pulse $(1$T$)$ and $5$T is after the fifth clock pulse$).$ Please show the values for all bits up to $5$ T$.$

Data Preset: $0000($you may assume these are the bit values at OT$)$

Data In: $1001($begin with the left$-$most Data In value$)$

Edge Triggered: Rising

$\backslash (\backslash$begin$\{$array$\}\{$llll$\}$d$\_\{3\}$ & d$\_\{2\}$ & d$\_\{1\}$ & d$\_\{0\}\backslash$end$\{$array$\}\backslash )$

Use a table like the one below for your answer:

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