Question $3[20$ Marks$]$

Aa$)$ Consider a single set in a cache that is $8-$way set associative, with the blocks which are $\backslash ($ A$,$ B$,$ C $\backslash ),$ D$,$ E$,$ F$,$ G$,$ and H as shown below. The corresponding LRU counters are also shown, where $\backslash ($ O $\backslash )$ is the least recently used.

What are the new contents of the cache, after we perform accesses to A $,$ then B $,$ then A again, $[10]$ then D$,$ then K$?$ Update the LRU counter on each access.

b$)$ Assume a direct map cache that has one line. The valid bit starts out at $0,$ the dirty bit starts out at $1$ and the tag starts out at A $,$ as shown in the table below.

The processor does the following sequence of accesses: It reads A $,$ reads B $,$ writes B $,$ reads C $,$ reads D $,$ writes D $.$

Show the new state of the cache after each of these accesses, also determine how many cache misses there are, and how many write$-$backs to memory will happen during the sequence. $\backslash ([6,2,2]\backslash )$

Question $4[20$ Marks$]$

a$)$ Associativity usually improves the miss ratio, but not always. With the aid of an example, give a short series of address references for which a two$-$way set$-$associative cache with LRU replacement would experience more misses than a direct$-$mapped cache of the same size.

b$)$ Given the following cache types and data addresses to be accessed, which cache will you use to process the given data, why?

Available Cache Types:

$1.$ A $4$ KB Direct$-$Mapped cache with with a $16$ byte line size

$2.$ A $16$KB $2-$way Set Associative cache with $32$ byte line size

Data address to be accessed $($in the given order$)$:

$0$x$00$B$248$AC$,0$x$5002$AEF$3,0$x$10203000,0$x$0023$AF$7$C