Question: A MIPS assembly code is shown below. The assembly code is executed using a 5 5 - stage MIPS processor and we

  A MIPS assembly code is shown below. The assembly code is executed 
 
using a 5-stage MIPS processor and we can actually decide the branch a little earlier, in ID instead
of EX. Answer the following questions:
Loop: sub $19,$19,$20
addi $9,$20,5
sw $9,0($21)
addi $10,$19,2
sll $10,$10,$3
add $10,$10,$21
addi $11,$20,1
sll $11,$11,3
add $11,$11,$21
Iw $11,0($11)
sub $9,$9,$11
sw $9,0($10)
beq $9,$0, Loop
addi $9,$12,2
a). How many clock cycles are needed to execute the code above? Assume there is no forwarding, no
branch prediction.
b). How many clock cycles are needed to execute the code above? Assume there is forwarding, no
branch prediction.
c). Reorder the above code to reduce the stalls (get the smallest number of stalls) without changing the
functionality. Assume there is forwarding and no branch prediction. How many clock cycles are needed
to execute the code above?

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To answer the questions related to the given MIPS code we need to analyze the execution of the instructions in a 5stage MIPS pipeline IF ID EX MEM and ... View full answer

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