Question $3(8$ points$)$: Suppose we are using register scoreboarding to dynamically schedule

code. We have four functional units with the following execution stage latencies:

Consider the following program:

At the start of the program, no register values are being computed by any functional units $($i$.$e$.,$

all registers are "ready"$).$ Suppose the first instruction $($I$1)$ issues on cycle $1$ and reads

operands on cycle $2.$ Answer the following questions.

Question $3-$a$)$ Which instructions are stalled in the issue stage?

Question $3-$b$)$ Which instructions are stalled in the read operands stage?

Question $3-$c$)$ On which cycle does each instruction write back?