Question $3)$ Suppose we are using register scoreboarding to dynamically schedule code. We

have three functional units with the following execution stage latencies:

Consider the following program:

At the start of the program, no register values are being computed by any functional units $($i$.$e$.,$ all

registers are "ready"$).$ Suppose the first instruction $($I$0)$ issues on cycle $1$ and reads operands on

cycle $2.$ Answer the following questions.

Q$3-1)$ Which instructions are stalled in the issue stage?

Q$3-2)$ Which instructions are stalled in the read operands stage?

Q$3-3)$ Which instructions are stalled in the write results stage?

Q$3-4)$ On which cycle does each instruction write back?