Question $3$: The following MIPS Code is executed using the MIPS pipeline architecture. Include all iterations of the loop. For the given code, write the Pipeline Implementation by resolving all the three hazards using stalls or Hardware, based on the provided assumptions for each part.

Start: addiu $s$1,$ $$0,01234$

addi $s$0,$ $$0,0122C$

Loop:

lb $t$1,0($$$s0)$

sb $t$1,2($$$s0)$

nor $t$2,$ $t$1,$ $t$1$

sb $t$2,0($$$s0)$

addi $$s0,$$$s0,4$

bne $$s0,$$$s1,$ Loop

Exit: addi $$s0,$$$0,0122C$

$($a$)$ Consider the following assumptions: $($only structural hazards are resolved in hardware, other hazards have to be resolved with stall$/$nop$.)$

There is separate instruction and data memory access.

Register read and write can happen within the same clock cycle.

There is NO Forwarding unit and NO Hazard detection Unit.

Use stall if an instruction is delayed after fetch.

Use nop if an instruction is delayed before fetch.

$($b$)$ Consider the following assumptions: $($structural and data hazards are resolved using hardware, other hazards have to be resolved with stall$/$nop$.)$

There is separate instruction and data memory access.

Register read and write can happen within the same clock cycle.

There is Forwarding unit. Show data forwarding between the correct stages, wherever necessary.

There is NO Hazard detection Unit, i$.$e$.,$ no resolution for control hazards in hardware.

Use stall if an instruction is delayed after fetch.

Use nop if an instruction is delayed before fetch.

$($c$)$ Consider the following assumptions: $($all hazards are resolved using hardware$)$

There is separate instruction and data memory access.

Register read and write can happen within the same clock cycle.

There is Forwarding unit. Show data forwarding between the correct stages, wherever necessary.

There is Hazard detection Unit to detect mispredictions and flush if necessary.

The $2-$bit branch prediction scheme is used with initial prediction being weakly Not Taken.

There is Branch target Buffer $($BTB$)$ containing target address for the branch instruction.

Use stall if an instruction is delayed after fetch.

Use nop if an instruction is delayed before fetch.