Question 4: (20 points) Design a synchronous BCD counter. Use negative edge-triggered D flip-flops provided with a clock. (i) Draw the state diagram of the counter (ii) Build the counter's state table showing the synchronous inputs of the T flip-flops as well Using Kamaugh maps, find the minimal sum-of-products form of the equations for the inputs to the flip-flops; assume the next states of the unused combinations to be "don't care states (iii) (iv) Draw the logic diagram of the counter (v) Modify your diagram (of (iv) to show how your DCB counter can be cleared when it reaches the value 7. Use active low clear and NAND gate