Question $4$

The hypothetical MINE instruction set was implemented using a $400-MHz$ machine. The MINE instruction set has three classes of instructions called $R,$ J and I. The implementation uses $4$ clock cycles for R$-$class instructions, $3$ clock cycles for J$-$class instructions, and $2$ clock cycles for I$-$class instructions. Two software vendors provided compilers for this machine. For the same benchmark $C$ program, the compilers generated the following instructions and classes. $($All numbers are in millions of instructions.$)$

$\backslash$table$[[$Vendor$\text{'}$s Compiler,R$-$class,J$-$class,I$-$class$],[$V$1$ compiler,$50,100,80],[$V$2$ compiler,$120,80,30]]$

If the hardware manufacturer based its specifications on MIPS $($Million Instructions Per Second$),$ which of the two compiler vendors it would favor? Show all your work.

$[$Hints: you might utilize the following equations.$]$

CPU clock cycles $={\displaystyle \underset{i=1}{\overset{n}{}}}(\frac{C}{P}$I $,C_1)$