The hypothetical MINE instruction set was implemented using a $400-$MHz

machine. The MINE instruction set has three classes of instructions called R$,$ J and I. The

implementation uses $4$ clock cycles for R$-$class instructions, $3$ clock cycles for J$-$class

instructions, and $2$ clock cycles for I$-$class instructions. Two software vendors provided

compilers for this machine. For the same benchmark C program, the compilers generated

the following instructions and classes. $($All numbers are in millions of instructions.$)$

If the hardware manufacturer based its specifications on MIPS $($Million Instructions Per

Second$),$ which of the two compiler vendors it would favor? Show all your work