Question $4$

Verilog conditional operators are inferred as a MUX$2$ cell with both a "true$-$case" input and a "false$-$case" input. Note that you can create complex MUX$-$trees by nesting conditional operators, replacing either or both the "true$-$case" and "false$-$case" inputs with another conditional operator.

$1.$ Convert the following MUX circuit into Verilog, and include both the Verilog code and a screenshot of the matching circuit generated by DigitalJS.

$2.$ Convert the following Verilog into a MUX circuit, which you can either hand$-$draw or create using software such as Inkscape or Draw.io$.$ You may use DigitalJS as a reference, but the circuit must be your own work.

$```$

wire $[1$:$0]$ truecase$2=($d$\_$i$==3)?$ c$\_$i : d$\_$i;

wire $[1$:$0]$ falsecase$2=($b$\_$i$==2)?$ c$\_$i : b$\_$i;

assign y$2\_$o $=($a$\_$i$==1)?($truecase$2)$ : $($falsecase$2)$;

$```$