Question $5$: a$.$ Consider the following assembly language code: IO: ADD R$4=$ R$1+$ RO; $11$: SUB R$9-$ R$3-$ R$4$; $12$: ADD R$4-$ R$5+$ R$6$; $13$: LOW R$2$ MEM$[$R$3+100)$: $14$: LDW R$2-$ MEM $[$R$2+0)$; $15$: STW MEMR$4+100]-$ R$2$; $16$: AND R$2-$ R$2$ & R$1$; $17$: BEQ R$9-$ Rl$,$ Target; IB: AND R$9-$ R$96$ R$1$; Consider a pipeline with forwarding, hazard detection, and I delay slot for branches. The pipeline is the typical $5-$stage IF$,$ ID$,$ EX$,$ MEM, WB MIPS design. For the above code complete the pipeline diagram below instructions on the left, cycles on top$)$ for the code. Insert the characters IF$,$ ID$,$ EX$,$ MEM, WB for each instruction in the boxes. Assume that there two levels of bypassing, that the second half of the decode stage performs a read of source registers, and that the first half of the write$-$back stage writes to the register file. Label all data stalls $($Draw an X in the box$).$ Label all data forwards that the forwarding unit detects King Saud University College of Computer and Information Sciences Computer Engineering Department $3$x Semester II$,1443$ H CEN$316,$ Computer Architecture Homework $4($arrow between the stages handing off the data and the stages receiving the data$).$ What is the final execution time of the code? Cycles $01234567891011121413$ IO $11121314$ IS $161718$