Question $9$

In a pipelined processor, what is the primary problem associated with control hazards, and how is it typically mitigated?

Control hazards occur when there is a conflict in the use of registers between instructions, and they are resolved by adding more registers to the pipeline.

Control hazards occur when the pipeline stalls due to dependencies between arithmetic operations, and are mitigated by using data forwarding techniques.

Control hazards arise when a branch instruction's target address is not known until a later stage in the pipeline, leading to incorrect instructions being fetched. They are mitigated by techniques such as branch prediction and instruction flushing.

Control hazards occur due to the delay in determining the correct target address of a branch instruction, and are typically mitigated by adding more stages to the pipeline.