Question: Question Given a MIPS processor working at a frequency of 2 G H z with a single - level cache ( L 1 cache )

Question
Given a MIPS processor working at a frequency of 2GHz with a single-level cache (L1 cache) divided into an instruction cache and a data cache. 2% of the instructions miss, as well as 4% of the data. 40% of the instructions perform a memory access to the data cache, and the miss penalty is 400 clock cycles (for both instructions and data). Assume that without cache misses, the average CPI (cycles per instruction) of the processor is 1.4. What will be the runtime of a program with 109 instructions given this question's data?
A. It is not possible to calculate with the given data (missing general CPI).
B.7.7[sec]
C.7.9[sec]
D.12.7[sec]
E.15.8[sec]
 Question Given a MIPS processor working at a frequency of 2GHz

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